Logical Equivalence Checking

Contents

1. Goals
2. Circuit Structure

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Goals

1. Verify the functionality for two simple boolean circuits.

Circuit Structure

Failure to follow this structure can result in grading of the lab to be delayed or incorrect.

Your main Digital circuit should be named as LogicalEquivalenceChecking. The following ports should be opened for the LogicalEquivalenceChecking:

Port Direction	Port Name	Active	Port Width (bits)
INPUT	A	-	1
INPUT	B	-	1
INPUT	C	-	1
INPUT	D	-	1
OUTPUT	Y_0	-	1
OUTPUT	Y_1	-	1
OUTPUT	Z_0	-	1
OUTPUT	Z_1	-	1
OUTPUT	F_0	-	1
OUTPUT	F_1	-	1

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Table of contents

• Logical Equivalence Checking