Booth’s Mu1/step2ltiplier

Contents

1. Goals
2. Circuit Structure

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Goals

1. Optimize the adder circuitry for the Booth’s multiplier

Circuit Structure

Failure to follow this structure can result in grading of the lab to be delayed or incorrect.

Your main Digital circuit should be named as BoothsMultiplierPart2. The following ports should be opened for the BoothsMultiplierPart2:

Port Direction	Port Name	Active	Port Width (bits)	Description
INPUT	CLK	Rising	1	Clock input used for controlling the multiplier
INPUT	CLR	High	1	Clears the multiplier to allow it for later reuse
INPUT	MULTIPLIER	-	13	13-bit signed decimal input as multiplier
INPUT	MULTIPLICAND	-	13	13-bit signal decimal input as multiplicand
OUTPUT	RESULT	-	26	26-bit signed decimal output as a result from your multiplication
OUTPUT	OP_DONE	-	2	The operation you have performed (addition, subtraction, or no-op)
OUTPUT	DONE	High	1	Set high when you have finished the multiplication

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Table of contents

• Add Unit Optimization